Translation lookaside buffer

Results: 83



#Item
41Microsoft PowerPoint - CPU Caches.ppt

Microsoft PowerPoint - CPU Caches.ppt

Add to Reading List

Source URL: www.aristeia.com

Language: English - Date: 2013-01-31 17:37:04
42High-Performance Microkernels and Virtualisation on ARM and Segmented Architectures Carl van Schaik† and Gernot Heiser†‡§ †  Open Kernel Labs

High-Performance Microkernels and Virtualisation on ARM and Segmented Architectures Carl van Schaik† and Gernot Heiser†‡§ † Open Kernel Labs

Add to Reading List

Source URL: www.ssrg.nicta.com.au

Language: English - Date: 2013-10-20 22:09:47
43Tech. Rep[removed]Using Simple Page Placement Policies to Reduce the Cost of Cache Fills in Coherent Shared-Memory Systems Michael Marchetti, Leonidas Kontothanassis, Ricardo Bianchini, and Michael L. Scott

Tech. Rep[removed]Using Simple Page Placement Policies to Reduce the Cost of Cache Fills in Coherent Shared-Memory Systems Michael Marchetti, Leonidas Kontothanassis, Ricardo Bianchini, and Michael L. Scott

Add to Reading List

Source URL: www.cs.rochester.edu

Language: English - Date: 2011-03-27 21:03:45
44Incorporating Memory Management into User-Level Network Interfaces Matt Welsh, Anindya Basu, Thorsten von Eicken Department of Computer Science Cornell University User-level network interfaces allow applications direct a

Incorporating Memory Management into User-Level Network Interfaces Matt Welsh, Anindya Basu, Thorsten von Eicken Department of Computer Science Cornell University User-level network interfaces allow applications direct a

Add to Reading List

Source URL: www.eecs.harvard.edu

Language: English - Date: 2003-03-27 14:17:09
45Cortex-A9 Microprocessor Unit Subsystem

Cortex-A9 Microprocessor Unit Subsystem

Add to Reading List

Source URL: www.altera.com

Language: English - Date: 2014-08-20 16:09:24
46RadixVM: Scalable address spaces for multithreaded applications Austin T. Clements, M. Frans Kaashoek, and Nickolai Zeldovich MIT CSAIL A BSTRACT

RadixVM: Scalable address spaces for multithreaded applications Austin T. Clements, M. Frans Kaashoek, and Nickolai Zeldovich MIT CSAIL A BSTRACT

Add to Reading List

Source URL: people.csail.mit.edu

Language: English
47Programming Model, Nios II Processor Reference Handbook

Programming Model, Nios II Processor Reference Handbook

Add to Reading List

Source URL: www.altera.com

Language: English - Date: 2014-02-14 18:17:39
48A Protected Block Device for Persistent Memory Feng Chen Louisiana State University [removed]  Michael P. Mesnier

A Protected Block Device for Persistent Memory Feng Chen Louisiana State University [removed] Michael P. Mesnier

Add to Reading List

Source URL: storageconference.us

Language: English - Date: 2014-06-07 16:49:20
491  A Pipelined Asynchronous Cache System Mika Nystr¨om, Andrew M. Lines, Alain J. Martin Abstract— We present the design of a pipelined cache system for use

1 A Pipelined Asynchronous Cache System Mika Nystr¨om, Andrew M. Lines, Alain J. Martin Abstract— We present the design of a pipelined cache system for use

Add to Reading List

Source URL: www.async.caltech.edu

Language: English - Date: 2008-06-02 20:27:46
50Memory Integration: Implementing the Memory Model in Hardware  J.P. Grossman ([removed])  The Problem: The memory model of early computers was simple: memory was external storage for data; data could

Memory Integration: Implementing the Memory Model in Hardware J.P. Grossman ([removed]) The Problem: The memory model of early computers was simple: memory was external storage for data; data could

Add to Reading List

Source URL: www.ai.mit.edu

Language: English - Date: 2001-05-13 17:32:54